1. Technical Field
The present invention generally relates to a semiconductor integrated circuit such as an integrated circuit (IC) or a large-scale integration (LSI), and more particularly to a semiconductor integrated circuit that operates on multiple supply potentials.
2. Related Art
In recent years, semiconductor integrated circuits such as ICs or LSIs used in various electronic equipments have become increasingly highly-integrated and achieved lower operation voltages so that a high-speed operation and low power-consumption can be realized for those equipments. However, in view of the properties that are device-specific, it is extremely difficult to lower the operating voltage of all semiconductor integrated circuits in a unified manner. Thus, there arise cases in which multiple semiconductor integrated circuits operating on different supply potentials are interconnected.
In order to cope with such cases, a semiconductor integrated circuit having an internal circuit that operates on a low supply potential and an output driver that operates on a high supply potential has been developed. An example of such a semiconductor integrated circuit thus operating on two types of supply potentials will be described below with reference to FIG. 1.
The semiconductor integrated circuit shown in FIG. 1 includes an internal circuit 10, level-shifting circuits 21 and 22, a power-on-control (POC) circuit 30, an N-channel MOS transistor 41, a P-channel MOS transistor 42, inverters 51 and 52, and an output driver 60. The output driver 60 is composed of a P-channel MOS transistor 61 and an N-channel MOS transistor 62.
The semiconductor integrated circuit is supplied with a low supply potential LVDD (e.g. 1.5 V), a high supply potential HVDD (e.g. 3.3 V) and a reference potential Vss. When fed with signals from the internal circuit 10, the level-shifting circuits 21 and 22 shift the levels of the signals, thereby respectively generating signals of the levels best suited respectively to the inverters 51 and 52 operating on the supply potential HVDD. After being inverted respectively by the inverters 51 and 52, these signals are fed to the respective gates of the transistors 61 and 62 included in the output driver 60. The output signals outputted from the drains of the transistors 61 and 62 are fed via a pad to an external circuit operating on a supply potential that is equal to or higher than the potential HVDD.
In such a semiconductor integrated circuit, there arise some cases in which the supply potential HVDD is fed even when the supply potential LVDD is not fed because the external circuit connected to the pad is in operation, for example. In such cases, a high-impedance state (inconstant electric potential) occurs in outputs from the internal circuit 10, generating an inconstant state in outputs from the level-shifting circuits 21 and 22. Then, there is a risk depending on the electric potential of those outputs in which both of the transistors 61 and 62 included in the output driver 60 may come to an on-state to cause a through-current to flow. To cope with such a situation, the transistors 41 and 42 are turned on to fix the input potentials of the inverters by having the POC circuit 30 output high-level POC signals and low-level inverted POC signals when the supply potential LVDD is not fed. Accordingly, the transistors 61 and 62 included in the output driver 60 are both turned off.
FIG. 5 is a circuit diagram showing the configuration of a related art POC circuit. The POC circuit includes a resistance R1 connected to the supply potential LVDD, P-channel MOS transistors QP61 and QP62 and N-channel MOS transistors QN61 and QN62 in series connection, P-channel MOS transistors QP71 and QP72 and a resistance R2 in series connection, a P-channel MOS transistor QP81 and an N-channel MOS transistor QN81 constituting an inverter A, and a P-channel MOS transistor QP91 and an N-channel MOS transistor QN91 constituting an inverter B.
The supply potential LVDD is low-level when it is not fed, so that the transistors QP61 and QP62 are in an on-state while the transistors QN61 and QN62 are in an off-state. Therefore, the inverter A, being inputted with high-level signals, outputs low-level inverted POC signals, while the inverter B, being inputted with low-level inverted POC signals, outputs high-level POC signals. The inverted POC signals are fed back positively to the transistor QP71 to further stabilize the state.
On the contrary, when the supply potential LVDD is fed, the relationship is reversed between the levels of each unit, with the inverter A outputting high-level inverted POC signals and the inverter B outputting low-level POC signals. However, when the supply potential LVDD is 1.5 V and the supply potential HVDD is 3 V, the source potential of the transistor QP61 is 3 V while its gate potential is 1.5 V. Therefore, the transistors QP61 and QP62 are precluded from being in an off-state and a through-current flows through the series-connected transistors QP61 and QP62 and QN61 and QN62. The larger the difference between the supply potentials LVDD and HVDD, the larger the through-current that flows. Related art methods reduce the through-current by lowering the capacities of the transistors QP61 and QP62 to supply currents. However, since special-size transistors are needed for that purpose, causing a burden on layout designing for semiconductor integrated circuits.
JP-A-9-252532 is a first example of related art. It discloses a supply voltage detecting circuit that, in controlling an increase in power consumption, automatically generates supply voltage classifying signals to be inputted to an electronic circuit that responds to various supply voltages. In FIG. 1 of the publication, a supply voltage sensing circuit 16A determines a reference voltage V3 to be low-level when a supply voltage VDDX is 5 V, while it determines the reference voltage V3 to be high-level when the supply voltage VDDX is 5 V. However, the publication discloses no idea about reducing a through-current that flows in a circuit when only one type of supply potential out of two is fed.
JP-A-5-136671 is a second example of related art. It discloses a level-detecting circuit that is embedded in a semiconductor integrated circuit and applied to a starter circuit, for example, that controls an internal circuit so that it is deactivated while a supply voltage is lower than a predetermined level. In FIG. 1 of the publication, level-detection is performed by dropping a supply voltage VCC by as much as the threshold voltages of three NMOS transistors and applying the lowered supply voltage VCC to the gate of an NMOS transistor 27, thus causing a drain voltage STTX to change in accordance with the gate voltage of the transistor 27. However, the publication discloses no idea, about reducing a through-current that flows when only one type of supply potential out of two is fed.
JP-A-2004-208108 is a third example of related art. It discloses an integrated circuit that is provided with a circuit block controlling supply of power during a standby or other operation and prevents through-currents that are caused by unstable signals outputted from the circuit block in which power supply is disconnected. In FIG. 1 of the publication, when a mask signal MASK is turned to “L”prior to a power-off operation for the circuit block 10, a node N1 is maintained at “L”by a latching circuit 24 composed of a NAND 24a and an inverter 24b. Thereafter, when a supply potential VDD1 is lowered to an “L”level through a power-off operation, output signals of the NAND 24a are fixed at “H”. Even if an unstable mask signal MASK is outputted from the circuit block 10 in this state, the level of the node Ni is maintained at “L”. Thus, gate circuits 21l to 21n remain closed, thereby preventing through-currents in a logical circuit 22, caused by unstable signals SIGl to SIGn from the circuit block 10. However, in cases where two types of supply potentials are fed to the integrated circuit, if the supply potential fed to the NAND 24a, for example, is higher than the supply potential VDD1, a large through-current will flow unless the capacity of the NAND 24a to feed currents is controlled to a large extent.
JP-A-2004-165993 is a fourth example of related art. It discloses an interface device with multiple power supplies in a semiconductor integrated circuit. The interface device determines the state of an internal circuit and controls through-currents and collision currents, even in a transitional state of a semiconductor device having multiple power supplies, where one power supply is already in an on-state while the other power supply is still in an off-state. In FIG. 1 of the publication, a transistor 10 feeds a supply voltage to a buffer circuit 12 in a transitional state where an internal power supply 15 is already in an on-state while an external I/O power supply 13 is still in an off-state. However, a through-current may flow in the buffer circuit 12 if an external terminal connected to the input of the buffer circuit 12 is in a floating state.